In recent years, following downsizing of a memory cell in a DRAM (Dynamic Random Access Memory), a gate length of a memory cell transistor is inevitably reduced. However, if the gate length is smaller, then the short channel effect of the transistor disadvantageously becomes more conspicuous, and sub-threshold current is disadvantageously increased. Furthermore, if substrate concentration is increased to suppress the short channel effect and the increase of the sub-threshold current, junction leakage increases. Due to this, the DRAM is confronted with a serious problem of deterioration in refresh characteristics.
As a technique for avoiding the above-stated problem, attention is paid to a fin field effect transistor (hereinafter, “fin-FET”) structured so that channel regions are formed to be thin each in the form of a fin in a perpendicular direction to a semiconductor substrate and so that gate electrodes are arranged around the channel regions (see Japanese Patent Application Laid-open No. 2006-100600). The fin-FET is expected to be able to realize acceleration of operating rate, increase in ON-current, reduction in power consumption and the like, as compared with a planer transistor.
A structure of a conventional fin-FET will be described below with reference to FIGS. 14A and 14B.
FIG. 14A is a general perspective view showing the structure of the conventional fin-FET, and FIG. 14B is a general cross-sectional view taken along a line A-A of FIG. 14A.
As shown in FIG. 14A, a trench 201t for STI (Shallow Trench Isolation) (hereinafter, “STI trench 201t”) is formed in a semiconductor substrate 200 and an element isolation film 2011 is buried in the STI trench 201t by a predetermined depth from a bottom of the STI trench 201t. A part of the semiconductor substrate 200 surrounded by the STI trench 201t and located above the element isolation insulating film 2011 becomes a fin-shaped active region 202. The active region 202 includes a central portion 202a and portions 202b and 202c located on both sides of the central portion 202a, respectively. A gate electrode 203 is formed to cover an upper surface and both side surfaces of the fin-shaped active region 202 in the central portion 202a of the fin-shaped active region 202.
By performing ion implantation into the active region 202 of the semiconductor substrate 200 with the gate electrode 203 used as a mask, a source region 202s and a drain region 202d are formed in the active region 202 and a channel region 202n is formed between the source region 202s and the drain region 202d as shown in FIG. 14B.
In the fin-FET structured as shown in FIGS. 14A and 14B, it is preferable to form the source region 202s and the drain region 202d to be deep so that three surfaces, i.e., an upper surface and two side surfaces of the central portion 202a of the active region 202 function as channels. Due to this, the ion implantation needs to be performed with high energy to form the source and drain regions 202s and 202d. 
However, if the ion implantation is performed with high energy so as to form the source and drain regions 202s and 202d, the source and drain regions 202s and 202d are diffused into the channel region 202n covered with the gate electrode 203 as shown in FIG. 14B. In such a fin-FET, if a gate length is smaller, a distance between the source and drain regions 202s and 202d shown as two-headed arrow in FIG. 14B is narrower, with the result that the short channel effect cannot be ignored.
To suppress OFF-current (Ioff) resulting from the short channel effect, a concentration of the channel region 202n may be increased. However, in a device, e.g., a DRAM memory cell, in which it is necessary to suppress junction leakage, if the concentration of the channel region is increased, junction electric field is deteriorated. The deterioration in junction electric field disadvantageously increases the junction leakage, resulting in deterioration in data holding characteristics.